Merged DRAM with Logic/Analog (MDLA) technology for single-chip solution

This paper describes a process integration of Merged DRAM (dynamic random a ccess memory) with Logic and Analog (MDLA) using high performance 0.35 mu m CMOS technology for the implementation of "System on a Chip". DRAM whose c ell size was 2.1 mu m(2) and analog cores were embedded in 0.35 mu m logic chip without sacrifice of transistor performance of logic circuitry. The ob tained values of I-dsaturation of NMOS/PMOS transistors were about 530 and 250 mu A/mu m at 3.3 V, respectively. Dual gate oxide process was developed to support 5 V operation as well as 3.3 V operation. The key process featu re of this study was that the aluminum alloy layer was used as a bit line i n DRAM cells on the contrary to the employment of polycide in the conventio nal DRAM technology. In this study, metal-insulator-metal (MIM) capacitor s cheme was employed for the applications in high-resolution analog cores. Th e low value of voltage coefficient of capacitance as low as 10 ppm/V could be achieved with MIM scheme.