Plasma-damage-free gate process using chemical mechanical polishing for 0.1 mu m MOSFETs

We propose a new transistor process called the Damascene gate process, wher e in a gate electrode is patterned by chemical mechanical polishing (CMP). In this process, source/drain implants are carried out by using a dummy gat e pattern as a mask and activation annealing is completed before the actual gate oxide formation. After removal of the dummy fate, fresh oxide and gat e electrode films are formed in grooves and the gate electrode film is patt erned by CMP. As a result, the gate electrode surface is completely planari zed and the sheet resistivity of the gate electrode is very uniform in a li ne width range from 0.2 mu m to 5 mu m. Metal-oxide-semiconductor-field-eff ect-transistors (MOSFETs) formed by the Damascene gate process were found t o show higher electron mobility, smaller threshold voltage deviation and lo wer subthreshold swing due to lower surface state density as compared with conventional transistors. Therefore, the Damascene gate process is promisin g for the fabrication of sub-quarter-micron MOSFETs.