Improved Ti self-aligned silicide technology using high dose Ge pre-amorphization for 0.10 mu m CMOS and beyond

Improved Ti self-aligned silicide (SALICIDE) technology for 0.1 mu m compli mentary metal-oxide-semiconductor (CMOS) using high dose pre-amorphization implantation (PAD is developed. High dose PAI with As and cc promotes the g rowth rate of silicidation on polycrystalline silicon gate even when its le ngth is reduced to 0.1 mu m. Thus it achieves low sheet resistivity at: nar row lines. In addition, the advantage of Ge over As as PAI species is confi rmed. Ge PAI does not affect the parasitic resistance increase of p channel metal-oxide-semiconductor field effect transistor (pMOSFET) or junction le akage characteristics because of its electrical neutrality and high solubil ity in silicon.