A new shallow trench isolation (STI) process wit a mini-spacer at the maski
ng nitride sidewall before silicon trench etching was proposed. With this m
ini-spacer, thicker corner liner oxide and a T-shaped trench oxide can be f
ormed simultaneously. The issue of oxide-recess at STI corner can be effect
ively reduced and larger process window for subthreshold kink free device w
ere obtained. The isolation capability and junction integrity were both imp
roved as compared with those of the conventional STI process. Reverse narro
w width effect as well as gate oxide integrity were also improved. This tec
hnology was employed for 0.13 mu m complementary metal oxide silicon (CMOS)
device fabrication.