New tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability?

This paper will start with a discussion of why probe yield (the number of g ood chips per silicon wafer) is so important to financial success in integr ated circuit manufacturing. Actual data will be quoted and a numerical exam ple shown. A simple model will be given to demonstrate the main factors inf luencing yield and the relationship between yield and reliability of the fi nal product. In the last few years a range of new tools have been deployed in manufacturing, and these have accelerated the pace of yield improvement thus increasing competitive pressures. These tools will be described, along with examples of their use. Topics will include in-line inspection and con trol, automatic defect classification and data mining techniques. A proposa l is made to extend these tools to the improvement of reliability of produc ts already in manufacturing by maintaining absolute chip identity throughou t the entire wafer fabrication, packaging and final testing steps. (C) 1999 Elsevier Science Ltd. All rights reserved.