Improved SRAM failure diagnosis for process monitoring via current signature analysis

SRAM's are frequently used as monitor circuits for defect related yield, du e to the ease of testing and the good correlation to the yield characterist ics of logic circuitry. For the identification of the failure/fault type an d the nature of the defect causing the failure, measured failbitmaps are ma pped onto a failbitmap catalog obtained from defect-fault simulation. Often this mapping is not unique. A given failbitmap can be caused by several fa ults or defects. In this contribution, the application of current signature analysis is demo nstrated for a stand-alone 16kx1 SRAM monitor circuit. It is found that the resolution of the failbitmap-fault-defect catalog can be improved consider ably by additional current signature measurements. The interpretation of cu rrent measurements is based on simulation of the possible faults contained in the failbitmap catalog under the operating conditions in the current tes t. There was good agreement between the simulated and measured current valu es. With the aid of current measurements, more yield learning information is ob tained from the process monitoring vehicle. In some cases, the shorted node s inside a SRAM cell can be determined exactly. This eases the localization of the failure and is of practical importance for the sample preparation i n physical failure analysis. (C) 1999 Elsevier Science Ltd. All rights rese rved.