Non-trivial GR and 1/f noise generated in the p-Si layer of SOI and SOS MOSFETs near the inverted front or buried p-Si/SiO2 interface

The nature of the non-trivial low-frequency (LF) current noise of both gene ration-recombination (GR) and 1/f type observed in accumulation and depleti on mode (AM/DM) p-MOSFETs and enhancement mode (EM) n-MOSFETs fabricated in silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) substrates is inve stigated, for gate biasing conditions where either the front or the back p- Si/SiO2 interface is in weak or strong inversion. The noise considered incr eases sharply with increasing positive gate voltage near the inversion thre shold and is very high under strong inversion conditions. For the GR noise, it has been shown that both the noise relaxation time tau and the spectral density S-1(0) at the low frequency plateau of the corres ponding Lorentzians are only determined by the inverting front (back) volta ge U-Gf,U-b in AM/DM p-MOSFETs, while the drain current is the main factor determining tau and S-1(0) in EM n-MOSFETs. As to the 1/f noise, a high sca tter in the data obtained in different samples has been observed in SOS DM p-MOSFETs and a correlation between the level of this noise and the behavio ur of the current has been revealed. Arguments are presented that the GR an d 1/f noise at stake are of a similar physical nature and are typical for d evices with an inverted p-Si/SiO2 interface. It is shown that the responsib le noise centres are located in a narrow layer of the p-type silicon film i n the close vicinity of the p-Si/SiO2 interface. A model to explain all non -trivial features of both the noise and the current is proposed and validat ed.