Efficient block scheduling to minimize context switching time for programmable embedded processors

Scheduling is one of the most often addressed optimization problems in DSP compilation, behavioral synthesis, and system-level synthesis research. Wit h the rapid pace of changes in modern DSP applications requirements and imp lementation technologies, however, new types of scheduling challenges arise . This paper is concerned with the problem of scheduling blocks of computat ions in order to optimize the efficiency of their execution on programmable embedded systems under a realistic timing model of their processors. We de scribe an effective scheme for scheduling the blocks of any computation on a given system architecture and with a specified algorithm implementing eac h block. We also present algorithmic techniques for performing optimal bloc k scheduling simultaneously with optimal architecture and algorithm selecti on. Our techniques address the block scheduling problem for both single- an d multiple-processor system platforms and for a variety of optimization obj ectives including throughput, cost, and power dissipation. We demonstrate t he practical effectiveness of our techniques on numerous designs and synthe tic examples.