An adiabatic differential logic for low-power digital systems

A new adiabatic circuit technique called adiabatic differential cascode vol tage switch with complementary pass-transistor logic tree (ADCPL) is presen ted. ADCPL is a dual-rail logic with relatively low gate complexity. It ope rates from a two-phase nonoverlapping supply clock. Power reduction is achi eved by recovering the energy in the recover phase of the supply clock, Ene rgy dissipation comparison with other logic circuits is performed, Simulati on shows that for a pipelined ADCPL carry lookahead adder, a power reductio n of 50%-70% can be achieved ol er the static complimentary metal oxide sem iconductor case within a practical operation frequency range. The results a lso show that the lower the operating frequency, the larger the energy savi ngs for an ADCPL circuit.