EJ-MOSFETs: Toward 10-nm-scale ultimately miniaturized MOSFETs

We fabricated electrically variable shallow junction MOSFETs for studying p hysical phenomena in MOSFETs. By using ultrafine lithography techniques, th e gate length of 14 nm was firstly achieved. In spite of such an ultrafine gate, the device operated at room temperature. The subthreshold swing was p roportional to temperature, indicating that the carrier transport mechanism was governed by the classical thermal process even in the 10-nm regime at room temperature.