S. Nikolaidis et A. Chatzigeorgiou, Modeling the transistor chain operation in CMOS gates for short channel devices, IEEE CIRC-I, 46(10), 1999, pp. 1191-1202
Citations number
17
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
A detailed analysis of the transistor chain operation in CMOS gates is intr
oduced. The chain is modeled by a transistor pair, according to the operati
ng conditions of the structure, The system of differential equations for th
e derived chain model is solved and analytical expressions which accurately
describe the temporal evolution of the output voltage are extracted. For t
he first time, a fully mathematical analysis without simplified step inputs
and linear approximations of the output waveform, and without resistors re
placing transistors, is presented. The width of the equivalent transistor t
hat replaces all nonsaturated devices is efficiently calculated, eliminatin
g previous inconsistencies in chain currents. A mapping algorithm for all p
ossible input patterns to a scheme that can be handled analytically is also
derived, The final results for the calculated response and the propagation
delay of this structure are in excellent agreement with SPICE simulations.