90 db, 90 MHz, 39 mW CMOS OTA for a high capacitive load

The design of simple gain-enhancement configurations for cascode transistor s is presented. Applying one- or two-stage differential amplifiers or an im proved regulated cascode configuration in the feedback loop of a cascode, a llows high-speed and high-gain super-transistors at low voltage to be desig ned, These concepts were implemented in a symmetrical OTA resulting in a me asured 90 dB, 90 MHz, 30 mW amplifier performance for a 14 pF load. Settlin g measurements to 0.1% error for a unity-gain configuration are presented. Copyright (C) 1999 John Wiley & Sons, Ltd.