CMOS SCALING INTO THE NANOMETER REGIME

Starting with a brief review on 0.1-mu m (100 nm) CMOS status, this pa per addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physic al effects and practical considerations. Among the issues discussed ar e: lithography, power supply and threshold voltage, short-channel effe ct, gate oxide, high-field effects, dopant number fluctuations, and in terconnect delays. The last part of the paper discusses several altern ative or unconventional device structures, including silicon-on-insula tor (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET 's, which may take us to the outermost limits of silicon scaling.