Realistic modelling of blocked packets for accurate performance evaluationof ATM switches

Multistage switches have been used as ATM switching fabrics in broadband IS DN networks, and also to connect processors to memories in massively parall el multiprocessor systems. Previous performance models for multistage switc hes have been neither accurate enough nor based on realistic assumptions re garding modelling the correlation of the blocked packets in successive stag es of the switch. Two new analytical models for accurate analysis of multis tage switches are proposed. The new models reflect the realistic behaviour of blocked packets, and take into account the fact that a blocked packet al ways hunts for the same output link in successive clock cycles. The results obtained from the models are more accurate than those available in the lit erature.