Understanding the limits of ultrathin SiO2 and Si-O-N gate dielectrics forsub50 nm CMOS

In spite of its many attributes such as nativity to silicon, low interfacia l defect density, high melting point, large energy gap, high resistivity, a nd good dielectric strength, SiO2 suffers from one disadvantage, low dielec tric constant (K=3.9). Thus, ultrathin SiO2 gate dielectric layers are requ ired to generate the high capacitance and drive current required of sub-50 nm transistors. The silicon industry roadmap dictates 4 nm SiO2 gate dielec trics for 0.25 mu m technology today, and calls for <1 nm equivalent SiO2 t hickness for 0.05 mu m technology in 2012. SiO2 layers in this thickness ra nge may suffer from boron penetration, reduced drive current, reliability d egradation, and high gate leakage current. We will argue that none of these problems are limitations for thicknesses greater than about 1.3 nm. Below that thickness, the fundamental problems of high tunneling current and redu ced current drive will prevent further scaling, unless alternate gate diele ctrics are introduced.