A novel low-temperature (Ba,Sr)TiO3 (BST) process with Ti/TiN barrier for Gbit DRAM applications

A new, low temperature (Ba,Sr)TiO3 (BST) MOCVD process has been established at 580 degrees C deposition temperature which can be used for Gbit DRAM ap plications using Ti/TiN as barrier material. The process window for BST dep osition was investigated in terms of deposition temperature, stoichiometry, film thickness, post annealing treatment and variation of the underlying e lectrode/barrier layer. Electrical characterization revealed specific capac itance values of 45 fF/mu m(2) for 25-30 nm film thickness and 75 fF/mu m(2 ) for 10 nm film thickness which is close to the target value for GBit of 8 0-100 fF/mu m(2). Oxidation resistance of the Ti/TiN barrier could be shown up to 600 degrees C. Feasibility of this low temperature BST process has b een successfully demonstrated using a 4 Mbit test vehicle.