Designing MOS/SOI transistors for high frequency and low voltage applications

With the development of digital SOI technologies for portable communication systems [1, 2], high frequency modelization and design efforts are necessa ry to take into account some specific SOI effects. In this paper we evaluat e the influence of the transistor design (process and geometry) on its freq uency performances. We particularly investigate the influence of gate lengt h and width, the adjunction of body ties to avoid floating body effects; an d the DTMOS structure [3-5] for low voltage applications.