Oxide scaling limit for future logic and memory technology

Citation
Jh. Stathis et Dj. Dimaria, Oxide scaling limit for future logic and memory technology, MICROEL ENG, 48(1-4), 1999, pp. 395-401
Citations number
25
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
MICROELECTRONIC ENGINEERING
ISSN journal
01679317 → ACNP
Volume
48
Issue
1-4
Year of publication
1999
Pages
395 - 401
Database
ISI
SICI code
0167-9317(199909)48:1-4<395:OSLFFL>2.0.ZU;2-2
Abstract
The limit of MOSFET oxide scaling is examined from the viewpoint of reliabi lity. Measurements of the voltage dependence of the defect generation rate and the thickness dependence of the critical defect density, together with the breakdown statistics for ultra-thin oxides, are used to provide a gener al framework for predicting the lifetime of ultra-thin oxides at operating voltage. It is argued that reliability is the limiting factor for oxide thi ckness reduction.