A new fast cell resequence mechanism for multipath ATM switches

A new cell resequence mechanism is proposed to restore the cell sequence in multipath ATM switches. Since the proposed mechanism uses per-VC logical q ueues which store only the cells belonging to the same VC, the mechanism ca n reduce processing time compared to conventional resequence mechanisms. Th e mechanism also has no limitation on the peak rate of VC's and needs no ar bitration function to select an output cell, The mechanism can be implement ed using a RAM buffer, a content addressable memory/random access memory (C AM/RAM) table, a controller, etc.