VLSI hardware architecture for complex fuzzy systems

This gaper presents the design of a VLSI fuzzy processor, which is capable of dealing with complex fuzzy inference systems, i.e., fuzzy inferences tha t include rule chaining. The architecture of the processor is based on a co mputational model whose main features are: the capability to cope effective ly with complex fuzzy inference systems; a detection phase of the rule with a positive degree of activation to reduce the number of rules to be proces sed per inference; parallel computation of the degree of activation of acti ve rules; and representation of membership functions based on alpha-level s ets. As the fuzzy inference can be divided into different processing phases , the processor is made up of a number of stages which are pipelined, In ea ch stage several inference processing phases are performed parallelly, Its performance is in the order of 2 MFLIPS with 256 rules, eight inputs, two c hained variables, and four outputs and 5.2 MFLIPS with 32 rules, three inpu ts, and one output with a clock frequency of 66 MHz.