Unified fully-pipelined VLSI implementations of the one- and two-dimensional real discrete trigonometric transforms

Authors
Citation
Wh. Fang et Ml. Wu, Unified fully-pipelined VLSI implementations of the one- and two-dimensional real discrete trigonometric transforms, IEICE T FUN, E82A(10), 1999, pp. 2219-2230
Citations number
24
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
09168508 → ACNP
Volume
E82A
Issue
10
Year of publication
1999
Pages
2219 - 2230
Database
ISI
SICI code
0916-8508(199910)E82A:10<2219:UFVIOT>2.0.ZU;2-1
Abstract
This paper presents unified VLSI architectures which can efficiently realiz e some widespread one-dimensional (1-D) and two-dimensional (2-D) real disc rete trigonometric transforms, including the discrete Hartley transform (DH T), discrete sine transform (DST), and discrete cosine transform (DCT). Fir st, succinct and unrestrictive Clenshaw's recurrence formula along with the inherent symmetry of the trigonometric functions are adequately employed t o render efficient recurrences for computing these 1-D RDTT. By utilizing a n appropriate row-column decomposition approach, the same set of recurrence s can also be used to compute both of the row transform and column transfor m of the 2-D RDTT. Array architectures, basing on the developed recurrences , are then introduced to implement these 1-D and 2-D RDTT. Both architectur es provide substantial hardware savings as compared with previous works. In addition, they are not only applicable to the 1-D and 2-D RDTT of arbitrar y size, but they can also be easily adapted to compute all aforementioned R DTT with only minor modifications. A complete set of input/output (I/O) buf fers along with a bidirectional circular shift matrix are addressed as well to enable the architectures to operate in a fully-pipelined manner and to rectify the transformed results in a natural order. Moreover, the resulting architectures are both highly regular, modular, and locally-connected, thu s being amenable to VLSI implementations.