Rethinking deep-submicron circuit design

Several independent sources forecast that in deep-submicron (DSM) process g eometries, 80 percent or more of the delays of critical paths will be direc tly linked to interconnect. This forecast is supported by the significant t iming-closure problems that are arising in current high-performance IC desi gns. Based on this, both industry and academia sense the need for a significant overhaul of current synthesis and physical-design methodologies. In the eme rging design scenario, traditional design flows will no longer be viable fo r any size of module or block of gates. Deep-submicron effects-particularly those relating to interconnects-have th us been billed as potential roadblocks to the continuation of Moore's law. Some effects, like the rising resistance-capacitance (RC) delay of on-chip wiring, noise considerations, reliability concerns, and increased power dis sipation, manifest themselves in both the devices (transistors) and the int erconnect, though not in ways previously anticipated. The authors consider the effects of both devices and interconnect. Their an alysis shows that interconnect delay actually decreases for DSM processes i n a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performa nce ASIC designs.