Current directions in automatic test-pattern generation

Test development can be tedious and time-consuming, sometimes stretching ov er several months for complex designs. In the past two decades, various tes t development automation tools have attempted to address this problem and r educe the bottleneck in the product's time to market. These tools, which automate dozens of tasks essential for developing adequa te tests, generally fall into four categories: design for testability (DFT) , test pattern generation, pattern-grading, and test program development an d debugging. The focus in this article is on automatic test-pattern-generat ion tools. Researchers have looked primarily at issues such as scalability, ability to handle various fault models, and how to extend the algorithms beyond Boole an domains to handle different abstraction levels. Their aims were to speed up test generation, reduce test sequence length, and minimize power consum ption. As design trends move toward nanometer technology, however, new ATPG proble ms are emerging. Current modeling and vector generation techniques must giv e way to new techniques that consider timing information during test genera tion, scale to larger designs, and can capture extreme design conditions. T he authors describe current ATPG techniques and efforts to adapt ATPG techn ology to handle deep-submicron faults and to identify design errors and tim ing problems during design verification.