A fault-tolerant architecture for ATM networks

The asynchronous transfer mode (ATM) is the transfer mode recommended for t he broad integrated service digital network (B-ISDN) by ITU-T. In this pape r, we propose a self-routing fault-tolerant switching architecture for ATM networks. The proposed architecture uses subswitches and extra links to pro vide alternative paths; hence, can tolerate multiple faults. Analytical res ults show that the total number of redundant paths increases exponentially as the size of the network increases. A simulation model is developed. Simu lation results indicate that the proposed architecture is much more fault-t olerant and cost-effective than those architectures found in the literature . Simulation results also illustrate that the proposed architecture still m aintains a high throughput with an acceptable cell delay time, even when th e number of faulty elements increases. (C) 1999 Elsevier Science B.V. All r ights reserved.