Design of novel high side power MOSFET based on HVIC process

A novel high side power MOSFET is presented, the design of which is based o n a modified 600 V CMOS process developed for lateral power devices. Simula tion results indicate that the blocking voltage is in excess of 550V. A sig nificant enhancement in the blocking voltage is realised by incorporating t he source within an n-buffer layer. The improvement can be attributed to th e increase in the 'punch-through' voltage of the vertical parasitic PNP tra nsistor. The transient characteristic of turn on is also analysed.