110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock

A simultaneous bidirectional transceiver logic (SBTL), for a 0.25 mu m CMOS embedded array, has a low-voltage-swing input hip-pop circuit and an outpu t dip-hop with a boundary scan to enable a 1.1-Gb/s data transfer per LSI p in with a 550-MHz system clock. Clock skew and jitter minimization enables high bandwidth in a phase-locked system. Measured latency time for transmis sion is less than 3.0 ns during simultaneous switching mode when the cable length is 18 cm, Average power consumption is 12 mW per pin at 550 MHz. A l ow-noise output buffer and a controlled collapse chip connection (C4)-based 1595-pin package with on-package capacitors achieve 100-byte data bus. The maximum data bandwidth per LSI is 110 GB/s.