A 130-mm(2), 256-mbit NAND flash with shallow trench isolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 m u m is achieved with 0.25-mu m STI. The memory cell is shrunk to 0.29 mu m( 2), which realizes a 130-mm(2), 256-Mbit flash memory, Peripheral transisto rs are scaled with memory cells in order to reduce fabrication process step s. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-mu s first access time in spite of long a nd tight pitch bit-line, A I-kbyte page mode with 35-ns serial data out rea lizes 25-Mbyte/s read throughput. An incremental step pulse with a bit bq b it verify scheme programs 1-k cells in 1-V Vt distribution within 200 mu s. That realizes 4.4-Mbyte/s programming throughput.