An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

An 18-Mbit CMOS pipeline-burst cache SRAM achieves a 12.3-Gbyte/s data tran sfer rate with 1.54-Gbits/pin I/O's. The SRAM is fabricated on a 0.18-mu m CMOS technology, The 14.3 x 14.6-mm(2) SRAM chip uses a 5.59-mu m(2). six-t ransistor cell. Circuit techniques used for achieving high bandwidth includ e fully self-timed array architecture, segmented hierarchical sensing with separated global read/write bitlines in different metal layers, a high-spee d data-capture technique, a reduced-swing output buffer, and a high-sensiti vity itp, high-bandwidth input buffer.