A 390-mm(2), 16-bank, l-Gb DDR SDRAM with hybrid bitline architecture

A 390-mm(2), 16-bank, 1-Gb, double-data-rate (DDR) synchronous dynamic rand om access memory (DRAM) (SDRAM) has been fabricated in fully planarized 0.1 75-mu m, gF(2) trench cell technology, The 1-Gb SDRAM employs a hybrid bitl ine architecture with 512 cells/local-bitline (LBL), Four LBL pairs are con nected through multiplexers to each sense amplifier (SA). Tao Of the LBL pa irs are coupled to the SA by wiring over tao other LBL pairs using hierarch ical bitlines, This results in a reduction of the number of the SA's to 1/4 , reducing the chip size by 6%. A hierarchical column-select-line scheme is incorporated with a hierarchical dataline (MDQ) architecture. This makes 1 6-bank organization possible while sharing hierarchical column decoders and second sense amplifiers. A hierarchical 8-b prefetch scheme employs four M DQ's for each read-write drive (RWD) and tao RWD's for each DQ, This reduce s the frequencies of the MDQ's and the RWD's to lis and 1/2, respectively. ii 1-V swing signaling on the RWD is used to reduce the burst current by 18 mA. The 1-V swing signaling is successfully converted to 2.1 V with self-t imed first-in, first-out circuitry, The hardware data demonstrate 400-Mb/s/ pin operation with a 16-mm TSOP-II package. Seamless burst operation at var ious frequencies has also been confirmed, These features result in a 1.6-Gb /s data rate for x 32 200-MHz DDR operation with a cell/chip area efficienc y of 67.5%.