A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism

A four-way very long instruction word, 312-MHz geometry processor with peri pheral component interconnect/accelerated graphic port bus bridge was imple mented in a 0.21-mu m, 2.5-V, three-layer-metal CMOS process. We adopted 1) a software bypass mechanism, 2) single-instruction multiple-data stream in structions, 3) four sets of floating-point multiply-add and accumulate exec ution units, 3) special condition code registers and a branch condition gen erator for a clipping operation, and 5) automatic clock delay tuning method ology. As a result of these features, we achieved a performance of 2.5 GFLO PS and 6.5 million polygons per second for a three-dimensional geometry pro cessor, which is the highest published performance as a single geometry pro cessor. The processor is applicable to computer-aided-design systems that r equire very high graphics performance.