A single-chip universal digital satellite receiver with 480-MHz IF input

This paper presents a complete single-chip universal digital satellite rece iver supporting all current DBS system standards. The mired-signal device a ccepts a modulated data stream at up to 90 Mbps and delivers a demodulated, error-corrected output data stream. The IC features an analog front end wi th 480-MHz intermediate-frequency downconversion and dual 8-bit analog-to-d igital converters, an all-digital BPSK/QPSK/OQPSK variable-rate receiver su pporting 1-45-MBaud operation with phase/frequency recovery, variable-rate digital filters, square-root Nyquist matched filters, acquisition and track ing loops, and a DVB/DSS/DigiCipher I/II-compliant concatenated Viterbi/Ree d-Solomon forward error correction decoder with on-chip deinterleaver RAM. All required clocks are generated on chip from a single reference crystal. The chip contains 1.2 million transistors in a die area of 22 mm(2) and was implemented in a single-poly 0.35-mu m CMOS process with four layers of me tal.