A single-chip universal cable set-top box/modem transceiver

Citation
Lj. D'Luna et al., A single-chip universal cable set-top box/modem transceiver, IEEE J SOLI, 34(11), 1999, pp. 1647-1660
Citations number
13
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
34
Issue
11
Year of publication
1999
Pages
1647 - 1660
Database
ISI
SICI code
0018-9200(199911)34:11<1647:ASUCSB>2.0.ZU;2-8
Abstract
A mixed-signal digital cable-TV transceiver IC containing two distinctly se parate quadrature amplitude modulation (QAM) receivers and a single QAM mod ulator has been designed. An integrated 10-b analog-to-digital converter (A ID) interfaces the first receiver directly to an analog signal. This receiv er demodulates 4/16/32/64/128/256-QAM signals carrying the television progr ams or cable modem data with a variable symbol rate from 1 to 7 MBaud. A 6- b AID is integrated to interface the second receiver to an analog signal. T his receiver, used by cable operators for access control, demodulates quadr ature phase shift keying (QPSK) signals with a variable symbol rate from 0. 75 to 1.6 MBaud. The upstream modulator provides two-way communication requ ired for interactive television or cable modem services. Capable of QPSK/16 -QAM modulation with a variable transmission rate up to 25 Mb/s, the modula tor also includes an integrated 10-b digital to-analog converter to provide radio-frequency analog output from 0 to 65 MHz. Both receivers and the tra nsmitter incorporate on-chip forward error correction compliant with multip le worldwide standards allowing global deployment. The carrier, phase, and timing recovery for each receiver is achieved with on-chip tracking loops. Adaptive decision feedback equalizers are incorporated to eliminate intersy mbol interference. The transmitter incorporates preamble prepending and pre equalization to facilitate reception. The device further integrates access control message separation, set-top box control circuitry, and a parallel m icroprocessor bus interface to boost system performance. The design employs a combination of semicustom and custom circuit design techniques for speed , mired-signal performance, and layout density. Fabricated in a single poly , four-layer-metal, 0.35-mu m standard CMOS process, the chip area is 64 mm (2). The device is packaged in a 256 tape ball grid array (TBGA), and dissi pates 3 W at 3.3 V.