Improved PAL-2N logic with complementary pass-transistor logic evaluation tree

In general, adiabatic circuits demonstrate significant power savings over c onventional CMOS. However, it is impractical to use adiabatic switching tec hnique to implement complex logic with many cascading stages as only one le vel of gates can be computed in every phase. In this article, an improved P AL-2N logic with complementary pass-transistor logic (CPL) evaluation tree (C-PAL) is proposed. Using the proposed logic together with the PAL-2N logi c, more than one level of gates can be computed within a single operating p hase. This helps to achieve a reduced latency for the proposed adiabatic ci rcuit. (C) 1999 Published by Elsevier Science Ltd. All rights reserved.