Design of a fast radix-4 SRT divider and its VLSI implementation

The design of a fast divider is an important issue in high-speed computing. The paper presents a fast radix-4 SRT division architecture. Instead of fi nding the correct quotient digit, an estimated quotient digit is first spec ulated. The speculated quotient digit is used to simultaneously compute the two possible partial remainders for the next step while the quotient digit is being corrected. Thus, this two-step process does not influence the ove rall speed. Since the decisionmaking circuits can be implemented with simpl e gate structures, the proposed divider offers fast speed operation. Based on the physical layout, the circuit takes 247ns for a double precision divi sion (56 bits for fraction part), where the 2 mu m CMOS technology in MAGIC is employed and simulated.