Wafer-scale diagnosis tolerating comparator faults

A promising application of comparison-based system-level diagnosis is the t esting of VLSI chips during manufacture. However, existing comparison model s essentially overlook the test invalidation owing to the physical faults i n the comparators. A comparison model is proposed that takes into account f aults affecting the comparators and the syndrome generation circuitry. A co mparator test session is described that is capable of detecting any combina tion of stuck-at faults in the diagnostic-circuitry. This test requires uni ts on the wafer to use independent test inputs which can be satisfied at a small wafer design cost.