CML and ECL: Optimized design and comparison

In this paper a pencil-and-paper optimized design for current mode logic (C ML) and emitter coupled logic (ECL) gates is proposed. The approaches are b ased on simple models which show errors lower than 20% as compared with Spi ce simulations. The optimization is performed in terms of bias currents, which give the min imum propagation delay, and it is demonstrated that at the cost of a 10% in crease in propagation delay we can reduce the power dissipation by 40%. Str ategies to optimize the transistor area of the CML gates are also discussed . A comparison between the optimized CML and ECL is made. It shows the advant age of the CML gate with respect to the ECL in terms of propagation delay. However, this feature of CML is paid for in terms of power dissipation. The simple models and the design strategies are validated by using both a t raditional and a high speed bipolar process, which have transition frequenc ies equal to 6 and 20 GHz, respectively.