On the yield of VLSI processors with on-chip CPU cache

Yield enhancement through the acceptance of partially good chips is a well- known technique [1], [2], [3]. In this paper, we derive a yield model for s ingle chip VLSI processors with partially good on-chip cache. Also, we inve stigate how the yield enhancement of VLSI processors with on-chip CPU cache relates with the number of acceptable faulty cache blocks, the percentage of the cache area with respect to the whole chip area, and various manufact uring process parameters as defect densities and the fault clustering param eter. One of the main conclusions is that the maximum effective yield is ac hieved by accepting as good, caches with a very small number of faulty cach e blocks. One of the main conclusions is that the maximum effective yield i s achieved by accepting as good, processor chips containing caches with a v ery small number of faulty cache blocks.