A high speed Sorting Processor ASIC for the RPC Trigger System of the CMS experiment

Authors
De Robertis, G Loddo, F Ranieri, A
Citation
G. De Robertis et al., A high speed Sorting Processor ASIC for the RPC Trigger System of the CMS experiment, NUCL INST A, 436(3), 1999, pp. 394-400
Citations number
4
Categorie Soggetti
Spectroscopy /Instrumentation/Analytical Sciences","Instrumentation & Measurement
Journal title
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT
ISSN journal
01689002 → ACNP
Volume
436
Issue
3
Year of publication
1999
Pages
394 - 400
Database
ISI
SICI code
0168-9002(19991101)436:3<394:AHSSPA>2.0.ZU;2-L
Abstract
The design of a high speed Sorting Processor ASIC is presented. It was desi gned in BiCMOS 0.8 mu m technology and its aim is to reorder and provide th e four highest words among eight input words, in decreasing order. This chi p is the main component of the sorting tree of the Trigger Muon System of t he CMS experiment. (C) 1999 Elsevier Science B.V. Ail rights reserved.