Analysis of ground-bounce induced substrate noise coupling in a low resistive bulk epitaxial process: Design strategies to minimize noise effects on a mixed-signal chip

The industry trend toward system-on-chip solutions continues to push the li mits of mixed-signal design, Increasing the integration of analog and digit al circuitry causes a struggle to maintain analog signal integrity. Digital switching of noise coupling through the common substrate is both difficult to measure and difficult to control. This paper introduces and applies a p ractical first-order simulation methodology for performing a substrate nois e analysis in a low resistive bulk process. Although this subject has been analyzed in numerous journal articles, few have applied their analysis meth od to a whole-chip design. This SPICE model will allow mixed-signal designe rs to determine design variables that will minimize substrate noise. This w ork elaborates on key aspects of substrate noise that available refer ences do not handle adequately, including: sources of substrate noise, determina tion of power-rail and bulk-resonance frequencies, and alternatives for bul k biasing. The new model is used to analyze Motorola's 56824, the latest lo w-cost 16-bit digital signal processor design. The analysis includes the de termination of: 1) the on-chip bus and I/O bus noise coupled to the substra te; 2) the dominant resonant frequencies in the chip; and 3) the best bulk- biasing alternative.