Improving dictionary-based code compression in VLIW architectures

Reducing code size is crucial in embedded systems as well as in high-perfor mance systems to overcome the communication bottleneck between memory and C PU, especially with VLIW (Very Long Instruction Word) processors that requi re a high-bandwidth instruction prefetching. This paper presents a new appr oach for dictionary-based code compression in VLIW processor-based systems using isomorphism among instruction words. After we divide instruction word s into two groups, one for opcode group and the other for operand group, th e proposed compression algorithm is applied to each group for maximal code compression. Frequently-used instruction words are extracted from the origi nal code to be mapped into two dictionaries, an opcode dictionary and an op erand dictionary. According to the SPEC95 benchmarks, the proposed techniqu e has achieved an average code compression ratio of 63%, 69%, and Sire in a 4-issue, X-issue, and 12-issue VLIW architecture, respectively.