High-level synthesis with SDRAMs and RAMBUS DRAMs

Newer off-chip DRAM families, including Synchronous DRAMs (SDRAMs) and RAMB US DRAMs (RDRAMs), are becoming standard choices for the design of high-per formance systems. Although previous work in High-Level Synthesis (HLS) has addressed exploiting features of page-mode DRAMs, techniques do not exist f or exploiting the two key features of these newer DRAM families that boost memory performance and help overcome bandwidth limitations: (1) burst mode access, and (2) interleaved access through multiple banks. We address pre-s ynthesis optimizations on the input behavior that extract and exploit the b urst mode and multiple bank interleaved access modes of these newer DRAM fa milies, so that these features can be exploited fully during the HLS trajec tory. Our experiments, run on a suite of memory-intensive benchmarks using a contemporary SDRAM library, demonstrate significant performance improveme nts of up to 62.5% over the naive approach, and improvements of up to 16.7% over the previous approach that considered only page-mode-or extended-data out (EDO) DRAMS.