Clock period minimization of semi-synchronous circuits by gate-level delayinsertion

A semi-synchronous circuit is a circuit in which every register is ticked b y a clock periodically, but not necessarily simultaneously. In a semi-synch ronous circuit, the minimum delay between registers may be critical with re spect to the clock period of the circuit, while it does not affect the cloc k period of an ordinary synchronous circuit. In this paper, we discuss a de lay insertion method which makes such a semi-synchronous circuit faster. Th e maximum delay-to-register ratio over the cycles in the circuit gives a lo wer bound of the clock period. We show that this bound is achieved in the s emi-synchronous framework by the proposing gate-level delay insertion metho d.