Internet-based hierarchical floorplan design

With the proliferation of the transistor count in VLSI design, more and mor e design groups try to figure out an efficient way to combine their designs . The Internet features distributed computing and resource sharing. Consequ ently, a hierarchical design can adequately be solved in the Internet envir onment. In this paper, we demonstrate the facilitation of the Internet envi ronment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of trans fer latencies, the RMG algorithm reduces the computing time by shortening t he critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).