Fast instruction cache simulation for hardware/software co-design

Cache memories are one of the main factors that affect software performance , and their use is becoming increasingly common even in embedded systems. E fficient analysis of the effects of parameter variations (cache size, degre e of associativity, replacement policy, line size,...) is at the same time an essential and very time-consuming aspect of embedded system design, whos e complexity increases when multi-tasking and real-time aspects must be con sidered. We propose a new simulation-based methodology, focused on an appro ximate model of the cache and of the multi-tasking reactive software, that allows one to trade off smoothly between accuracy and simulation speed. In particular, we propose to accurately consider intra-task conflicts, but app roximate inter;task conflicts by considering only a finite number of previo us task executions. The rationale for this choice can be found in a common pattern in embedded systems, where a "normal" data flow results in a regula r intra-task common flow, interrupted from time to time by some urgent even t, that pessimistically can be considered as disrupting the cache behavior. The approach is conservative because re-execution of a task after a large amount of time will always be considered as not in cache, and the simulatio n speed-up is considerable.