A high-speed, low-power phase frequency detector and charge-pump circuits for high frequency phase-locked loops

In this paper, we introduce a high-speed and low-pou er Phase-Frequency Det ector (PFD) that is designed using a modified TSPC (True Single-Phase Clock ) positive edge triggered D flip-Rep. The proposed PFD has a simple structu re with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD h as a dead zone less than 0.01 ns in the phase characteristics and has low p hase sensitivity errors. The phase and frequency error detection range is n ot limited as in the case of the pt-type and nc-type PFDs [3]. Also, the PF D is independent of the duty cycle of input signals. Also, a new charge-pum p circuit is presented that is based on a charge-amplifier. A stand-by curr ent of the proposed charge-pump circuit enhances the speed of charge-pump a nd removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the propo sed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 mu m CMOS technology with 5 V supply voltage.