A new single-clock flip-flop for half-swing clocking

A new hip-hop configuration for half-swing clocking is proposed to save tot al clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or a ny additional logics which were used in the earlier half-swing clocking sch emes. V-cc is supplied to the random logic circuits and flip-flops while V- cc/2 is supplied to the clock network and some parts of the Aip-flop to red uce the power consumed in the clock network. Compared to the conventional s cheme, the proposed flip-flop configuration can save the clocking power by 40%.