A method of generating tests with linearity property for gate delay faultsin combinational circuits

A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under tes t is a marginal chip or not [1]. The latest transition time at the primary output is changed linearly with the size of the gate delay Fault when the p roposed test is applied to the circuit under test. To authors' knowledge, n o reports on an algorithmic method for generating tests with linearity prop erty have been presented before. In this paper, we propose a method for gen erating tests with linearity property for gate delay faults. The proposed m ethod introduces a new extended timed calculus to calculate the size of a g iven gate delay fault that can be propagated to the primary output. The met hod has been applied to ISCAS benchmark circuits under the unit delay model .