An experimental high speed 1:4 demultiplexer integrated circuit featur
ing output bit alignment, reduced gale count, and a never circuit arch
itecture is presented. The experimental circuit features an inherently
fast two-stage configuration, with operation at up to 30 Gbit/s demon
strated in an advanced AlGaAs/GaAs heterojunction bipolar technology.
The system dock frequency is half the bit rate with only one additiona
l self-generated internal clock necessary.