Trade-off and process consideration for scalable poly-Si buffered LOCOS technology

The trade-off and process consideration for the scalable usage of poly-Si b uffer LOGOS (PBL) technology has been studied. By using a proper stack laye r of pad-oxide/poly-Si/nitride, an available and reliable PBL process for s calable device isolation can be achieved. A dual mechanism for pit formatio n is proposed. As the thermal stress is too large to be sustained by the pa d poly-Si, stress-induced voids are found in the poly-Si layer after field oxidation. The residual stress would considerably damage the pad oxide, eve ntually leading to pit formation at the mostly stressed active area while r emoving the pad poly-Si. On the other hand, when the stress is not sufficie ntly high, the pad poly-Si is just subject to stress-enhanced oxy-nitridati on. A proper etching control can be employed to retain the integrity of Si substrates. As results, thicker nitride induces larger stress and thus much more easily causes pit formation. Moreover, thicker pad poly-Si can sustai n larger stress, but degrade the drain-induced barrier lowering for the fie ld isolation device. Hence, the choice of the PBL stack layer is of great i mportance to reduce the bird's beak encroachment and alleviate the pit form ation as well as retain the gate oxide integrity and the isolation performa nce. (C) 1999 Elsevier Science Ltd. All rights reserved.