Instruction cache prefetching directed by branch prediction

As the gap between processor speed and memory speed grow, so the performanc e penalty of instruction cache misses gets higher. Instruction cache prefet ching is a technique to reduce this penalty. The prefetching methods determ ine the target line to be prefetched generally based on the current fetched line address. However, as the cache line becomes wider, it may contain mul tiple branches. This is a hurdle which must be overcome. The authors have d eveloped a new instruction cache prefetching method in which the prefetch i s directed by the prediction on branches, called branch instruction based ( BIB) prefetching; in which the prefetch information is recorded in an exten ded BTB. Simulation results show that for commercial benchmarks, BIB prefet ching outperforms traditional sequential prefetching by 7% and other predic tion table based prefetching methods by 17% on average. As BTB designs beco me more sophisticated and achieve higher hit and accuracy ratios, BIB prefe tching can achieve a higher level of performance.